Intel Foundry

Santa Clara, CA, USA (division of Intel Corporation)

Company Overview

Headquarters: Santa Clara, CA, USA (division of Intel Corporation)
Ownership: Public (Nasdaq: INTC); US government holds ~10% equity (~$8.9B, 433.3M shares) via CHIPS Act conversion since Aug 2025; SoftBank ~2%
Leading-Edge Fab Locations: Chandler, AZ (Fab 52 — 18A high-volume manufacturing since ~Oct 2025); Hillsboro, OR (Fab 25 — 18A HVM); Rio Rancho, NM (advanced packaging); New Albany, OH (Module 1 — construction delayed, completion now targeted ~2030, not yet running any node)
Wafer Size: 300mm
Most Recent Revenue: Intel Foundry has been a reported segment since the Apr 2024 resegmentation. Q2 2026 segment revenue US$5.8B (+31% YoY), of which external revenue US$293M; FY2024 external revenue US$385M
Employees: Not broken out for Foundry; Intel-wide headcount ~85,100 as of Dec 27, 2025 (FY2025 10-K), down from ~109,000 a year earlier
Major Segments: Internal CPU/GPU (Panther Lake on 18A), external foundry customers (18A-P drawing 'inbound interest'), aerospace/defense-adjacent (Rio Rancho)
Long-Term Strategy: 18A in HVM since 2H2025 with yield improving ~7-8%/month (85% as of mid-2026); pursuing 14A with first-mover access to ASML High-NA EUV; actively courting external customers as part of 'IDM 2.0' foundry transformation

Process	Family	Architecture	Status	Details
Intel 18A-P2026 · 300mm	Gate-all-around	RibbonFET gate-all-around	Risk production	Performance-enhanced 18A with PowerVia. 9% higher performance at iso-power, or 18% lower power at iso-performance, vs Intel 18A. Entered risk production as of June 2026.AI compute, high-performance logic
Intel 18A2025 · 300mm	Gate-all-around	RibbonFET gate-all-around	Volume production	PowerVia backside power delivery. Entered production 2025; Intel announced high-volume manufacturing on 30 January 2026.AI compute, client and server logic

Most Advanced Node in HVM (mid-2026): 18A (RibbonFET GAA + PowerVia backside power) — HVM since 2H2025, shipping in Panther Lake
Node Range Offered (≤22nm): Intel 7 → Intel 4 → Intel 3 → 20A → 18A → 14A
Transistor Architecture: GAA (RibbonFET) since 18A
Backside Power Delivery: Yes — PowerVia, industry's first in HVM at this class
In-House Advanced Packaging: Yes — Foveros, EMIB
HBM Integration Support: Yes
Automotive/Defense-Qualified Advanced Node: Verify — Rio Rancho/CHIPS-funded sites support aerospace/defense-adjacent work
Reported Yield (Most Advanced Node): ~85% at 18A and improving ~7-8%/month (KeyBanc data, mid-2026); ~5 points behind TSMC N2's ~90%
Reported Density (Most Advanced Node): 238 million transistors/mm² (TechInsights) — below N2's density but ranked highest on TechInsights' performance-per-node scale (2.53 vs. 2.27 N2 vs. 2.19 SF2)
Next-Node Roadmap: 14A — first to receive ASML's High-NA EUV scanner (delivered Dec 2025); targeting 2026-27, with select Panther Lake layers already dual-qualified on High-NA tools

Qualified Leading-Edge Fabs: 4 (Chandler AZ, Rio Rancho NM, Hillsboro OR, New Albany OH)
Multi-Site Technology Transfer: Yes — internal IDM transfer plus CHIPS-funded Ohio ramp
Automotive/Defense Production: Yes — Rio Rancho and broader network support aerospace/defense-adjacent work; long-standing US secure/trusted-supply relationships
IATF 16949: Verify
Other Certifications: Verify
Export Restriction Status: Entirely US-based for leading-edge; not export-restricted; most CHIPS-Act-aligned of the three Western players

Backlog / Lead Time: External Foundry backlog reported >$15B
Utilization & Yield Maturity: 18A yield ~85% and improving ~7-8%/month; roughly 5 points behind TSMC N2's ~90%
Expansion Plans: New Albany, OH Module 1 (18A, 30,000 wpm) in volume; 14A development with first High-NA EUV access
Geographic Redundancy: Good — entirely US-based for leading-edge (Arizona, New Mexico, Oregon, Ohio)
Single-Site Concentration Risk: Low — genuinely multi-site within the US
Natural Disaster Exposure: Low — US Midwest/Southwest sites, though Arizona water-use scrutiny is an ongoing industry-wide consideration

Fab Site	Country	US Import Tariff	Considerations	Risk
Chandler AZ (Fab 52, 18A HVM) / Hillsboro OR (Fab 25, 18A HVM) / Rio Rancho NM (advanced packaging) / New Albany OH (delayed to ~2030, not yet operating)	United States	Not recorded	CHIPS Act award finalized at $7.86B (Nov 2024), with $5.7B of it accelerated ahead of schedule in Aug 2025; entirely domestic leading-edge footprint	Low

Approx. 300mm Wafer Price (Most Advanced Node): Intel Foundry Services (IFS) quotes external-customer rates separately from internal-use costs; not detailed in current source set — verify directly
Approx. Mask Set Cost (Most Advanced Node): Not detailed in current source set — verify directly
Approx. Full Tapeout Cost (Design + Mask + NRE): Not detailed in current source set — verify directly
MPW / Small-Program Access: Emerging — Intel is actively courting external customers (18A-P 'inbound interest') but does not yet have an established small-program/MPW track record at this tier
Pricing Position: Positioning to compete on performance-per-watt and US/CHIPS-Act-aligned sourcing rather than on being the lowest-cost option
Packaging Cost Add-On (CoWoS/HBM-Class): Foveros/EMIB packaging economics not separately benchmarked in current source set

Cadence: Yes
Synopsys: Yes
Siemens EDA (Calibre): Yes — Calibre standard sign-off
Own Ecosystem Program: IFS Accelerator program (IP alliance, chiplet/design ecosystem, cloud/EDA partnerships)
IP Vendor Relationships: Actively expanding third-party IP catalog; historically smaller than TSMC's but growing
Advanced Packaging Partners: In-house Foveros/EMIB; increasingly promoted to external customers
Notable Ecosystem Note: The newest large-scale external-facing ecosystem of the three Western players — actively being built out, not yet as deep as TSMC's OIP