Rapidus

Tokyo (Chiyoda-ku), Japan; Chitose, Hokkaido (fab/R&D); Santa Clara, CA (Rapidus Design Solutions)

Company Overview

Headquarters: Tokyo (Chiyoda-ku), Japan; Chitose, Hokkaido (fab/R&D); Santa Clara, CA (Rapidus Design Solutions)
Ownership: Private consortium (Toyota, Sony, NTT, NEC, SoftBank, MUFG, Kioxia, Denso, and others) plus heavy Japanese government (METI/NEDO) backing
Leading-Edge Fab Locations: IIM-1 — Chitose, Hokkaido, Japan (single fab, opened April 1, 2025)
Wafer Size: 300mm
Most Recent Revenue: FY2025 net loss ¥375 million on total assets of ¥749.5 billion (pre-revenue startup); ¥267.6B ($1.7B) funding round closed Feb 2026; lifetime investment expected to exceed ¥7 trillion, ~¥5 trillion needed to reach stable 2nm production
Employees: 1,024 as of December 1, 2025 (company profile)
Major Segments: Targeting AI/HPC chiplet customers, defense contractors, and academic/research programs underserved by large-volume-oriented big fabs (Canon and Synopsys are named trial customers)
Long-Term Strategy: First new leading-edge entrant in decades; single-wafer 'Rapid and Unified Manufacturing Service' flow (vs. batch processing) aims for faster AI-driven yield learning; targeting 2nm risk production 2027 / volume H2 2027; already planning 1.4nm (construction 2027, mass production ~2029) with IBM and imec

No named process technologies recorded for this foundry yet.

Absence here means the process list has not been researched, not that the foundry offers none.

Most Advanced Node in HVM (mid-2026): 2nm GAA (nanosheet, IBM technology transfer) — pilot/prototype only, not in production. Pilot line began operating April 2025; first 2nm GAA transistor demonstrated July 2025
Node Range Offered (≤22nm): 2nm only (no earlier nodes; 1.4nm in development)
Transistor Architecture: GAA nanosheet (IBM technology transfer)
Backside Power Delivery: Not confirmed for the initial 2nm process
In-House Advanced Packaging: New — Rapidus Chip packaging/analysis center opened April 2026; chiplet packaging R&D funded by NEDO
HBM Integration Support: Not yet in production
Automotive/Defense-Qualified Advanced Node: No — pre-production
Reported Yield (Most Advanced Node): Not yet published; company claims prototypes meet 'expected electrical characteristics' only
Reported Density (Most Advanced Node): 237 million transistors/mm² claimed for the 2HP process (unverified at production scale)
Next-Node Roadmap: 1.4nm process development starts 2026, fab construction 2027, mass production targeted ~2029 (with IBM and imec, using High-NA EUV)

Qualified Leading-Edge Fabs: 1 (Chitose, Hokkaido)
Multi-Site Technology Transfer: Yes — explicit technology transfer from IBM's Albany NanoTech Complex to Hokkaido, with Rapidus engineers having trained at Albany
Automotive/Defense Production: No — pre-production, no qualified automotive/defense output yet
IATF 16949: N/A (pre-production)
Other Certifications: N/A (pre-production)
Export Restriction Status: Not export-restricted; benefits from close Japan-US-Europe (IBM, imec) technology collaboration framework and Japanese government backing

Backlog / Lead Time: Pre-production; 2nm PDK reached early customers in Q1 2026; no confirmed production yield or backlog
Utilization & Yield Maturity: Not applicable — company has not yet reached volume production
Expansion Plans: Single IIM-1 fab targeting ~25,000 wpm at full ramp; 1.4nm fab construction planned to start 2027
Geographic Redundancy: None — single fab, single company, single country
Single-Site Concentration Risk: Highest in this list — the entire company's production capability is one fab
Natural Disaster Exposure: Japan is seismically active nationally; Hokkaido's specific profile differs from Honshu's, but general Japan earthquake risk applies

Fab Site	Country	US Import Tariff	Considerations	Risk
IIM-1 — Chitose, Hokkaido	Japan	Not recorded	Low direct trade/export risk as a US-aligned, IBM/imec-partnered project; the material risk here is business/execution viability (unproven yield, ¥7T+ lifetime investment need) rather than geopolitics	Low-Moderate

Approx. 300mm Wafer Price (Most Advanced Node): No public pricing — pre-commercial
Approx. Mask Set Cost (Most Advanced Node): No public pricing — pre-commercial
Approx. Full Tapeout Cost (Design + Mask + NRE): No public pricing — pre-commercial
MPW / Small-Program Access: This is Rapidus's explicit differentiator — the company markets a single-wafer, agile-turnaround model aimed at small-lot AI/HPC/defense/academic customers who can't get attention from TSMC/Samsung/Intel at scale
Pricing Position: Unknown — heavily government-subsidized at this stage; commercial pricing model has not been publicly disclosed
Packaging Cost Add-On (CoWoS/HBM-Class): New packaging/analysis center opened April 2026; cost structure not yet public

Cadence: Limited — early-stage relationships
Synopsys: Yes — Synopsys is an explicit named trial customer for Rapidus's 2nm process
Siemens EDA (Calibre): Yes — NYCREATES/Albany collaboration links Rapidus to Siemens-affiliated tooling and process work
Own Ecosystem Program: No formal named program yet; relies on IBM (technology transfer) and imec (Core Partner Program membership) rather than a proprietary ecosystem brand
IP Vendor Relationships: Nascent — IBM 2nm IP, imec R&D ties; Canon is a named trial customer for packaging/analysis services
Advanced Packaging Partners: New Rapidus Chip packaging/analysis center (opened April 2026); NEDO-funded chiplet packaging R&D
Notable Ecosystem Note: The ecosystem here is really 'IBM + imec + a handful of named trial customers' rather than a mature third-party marketplace — appropriate for a company still in pre-production