Samsung Foundry

Hwaseong / Pyeongtaek, South Korea (Samsung Electronics Device Solutions division)

Company Overview

Headquarters: Hwaseong / Pyeongtaek, South Korea (Samsung Electronics Device Solutions division)
Ownership: Public parent (Samsung Electronics, KRX: 005930)
Leading-Edge Fab Locations: Hwaseong & Pyeongtaek (Korea); Taylor, Texas (Fab 1 — SF2/2nm, risk production ~Feb 2026, Tesla AI5 production from Jul 2026, CHIPS-funded)
Wafer Size: 300mm
Most Recent Revenue: Samsung does not disclose Foundry-segment revenue. TrendForce estimates FY2025 Foundry revenue ~US$12.63B (-3.9% YoY); market share fell 9.4% to 7.2%
Employees: Not disclosed for Foundry alone; whole Device Solutions Division (memory + foundry + System LSI) ~78,064 at end-2025
Major Segments: Mobile SoC (Exynos), HBM-adjacent logic, automotive (Tesla), aerospace/defense (via Austin FD-SOI)
Long-Term Strategy: Broadening its order base around a proven, stable 4nm FinFET process for cost/reliability-focused customers rather than competing head-on at the bleeding edge; pushed sub-1nm target back ~2 years to 2029; deploying High-NA EUV in parallel with Intel

No named process technologies recorded for this foundry yet.

Absence here means the process list has not been researched, not that the foundry offers none.

Most Advanced Node in HVM (mid-2026): SF2 (2nm-class GAA) — mass production since Q4 2025 (official MP Nov 3, 2025; Exynos 2600 ramp Sept-Nov 2025). The "rebadged SF3P" characterization traces to a disputed Mar 2024 report Samsung never confirmed
Node Range Offered (≤22nm): SF4 (mature/stable) → SF3 (first commercial GAA, 2022) → SF2
Transistor Architecture: GAA nanosheet since SF3 (2022)
Backside Power Delivery: In development for future nodes — not yet in HVM
In-House Advanced Packaging: Yes — I-Cube/X-Cube-class packaging (verify current branding)
HBM Integration Support: Yes — 2nm applied to HBM per March 2026 disclosure
Automotive/Defense-Qualified Advanced Node: Yes — via Austin, TX FD-SOI expansion (aerospace/defense/automotive)
Reported Yield (Most Advanced Node): SF2: 50-60% (KeyBanc data) — 'far from commercial scale for merchant customers'
Reported Density (Most Advanced Node): Below TSMC N2 per TechInsights composite scoring (2.19 vs. 2.27 N2, 2.53 Intel 18A)
Next-Node Roadmap: Sub-1nm target pushed back from 2027 to ~2029; deploying High-NA EUV on 2nm lines in parallel with Intel

Qualified Leading-Edge Fabs: 3 (Hwaseong, Pyeongtaek, Taylor TX — ramping)
Multi-Site Technology Transfer: Yes — Korean engineers actively dispatched to Taylor, TX to support volume ramp
Automotive/Defense Production: Yes — Austin, TX FD-SOI expansion explicitly targets aerospace, defense, and automotive
IATF 16949: Verify
Other Certifications: Verify
Export Restriction Status: Korea/US sites not export-restricted; benefits from US CHIPS Act award

Backlog / Lead Time: 3nm/2nm customer adoption has been slowed by yield issues relative to TSMC's faster ramp
Utilization & Yield Maturity: 4nm mature and stable; SF2 (2nm) yield at 50-60%, not yet at merchant scale
Expansion Plans: Taylor, TX Fab 1 (3nm GAA, 15,000 wpm) ramping plus an on-site R&D fab several generations ahead; Austin FD-SOI expansion
Geographic Redundancy: Improving — Korea + Taylor, TX; still majority Korea-based today
Single-Site Concentration Risk: Moderate — concentrated in Korea with a growing but still small US footprint
Natural Disaster Exposure: Low-moderate (Korea); low (Texas, though regional grid/weather events have affected chip fabs there before)

Fab Site	Country	US Import Tariff	Considerations	Risk
Hwaseong & Pyeongtaek	South Korea	Not recorded	US treaty ally; Samsung-specific risk factors include labor union issues and execution/yield challenges more than direct trade-policy exposure	Moderate
Taylor, Texas (Fab 1 — SF2/2nm, Tesla AI5 production from Jul 2026)	United States	Not recorded	CHIPS Act award finalized at $4.745B (reduced from a proposed $6.4B after Commerce due-diligence review); 2nm GAA target	Low

Approx. 300mm Wafer Price (Most Advanced Node): Estimated ~20-25% below equivalent TSMC nodes per competitive-analysis estimates (not a published price list)
Approx. Mask Set Cost (Most Advanced Node): Comparable order of magnitude to TSMC at the same node; not separately benchmarked in current source set
Approx. Full Tapeout Cost (Design + Mask + NRE): Comparable order of magnitude to TSMC, adjusted for Samsung's lower quoted wafer price
MPW / Small-Program Access: Limited — Samsung Foundry engages primarily at volume-production scale; smaller programs are uncommon
Pricing Position: Value/cost-competitive positioning — actively used to win customers who prioritize price and stability over the most advanced node
Packaging Cost Add-On (CoWoS/HBM-Class): Comparable to TSMC for equivalent HBM/packaging integration; company-specific figures not detailed in current source set

Cadence: Yes
Synopsys: Yes
Siemens EDA (Calibre): Yes — Calibre standard sign-off
Own Ecosystem Program: SAFE (Samsung Advanced Foundry Ecosystem)
IP Vendor Relationships: Growing certified IP base; leverages Samsung's own memory/HBM expertise as a differentiator
Advanced Packaging Partners: I-Cube/X-Cube-class in-house packaging (verify current branding); external OSAT partners
Notable Ecosystem Note: Ecosystem is smaller than TSMC's but increasingly leverages Samsung's captive memory/HBM position as a selling point