← Leading-Edge Digital
TSMC
Hsinchu, Taiwan
Company Overview
- Headquarters
- Hsinchu, Taiwan
- Ownership
- Public (TWSE: 2330 / NYSE: TSM)
- Leading-Edge Fab Locations
- Fab 12 & Fab 20 (Hsinchu), Fab 14 & Fab 18 (Tainan), Fab 22 (Kaohsiung), Fab 15 (Taichung, mixed), Fab 21 (Phoenix AZ, US), ESMC (Dresden, Germany), Fab 16 (Nanjing, China, 16/12nm). Fab 23 Phase 2 (Kumamoto, Japan) construction paused late 2025, mass production now ~2029
- Wafer Size
- 300mm
- Most Recent Revenue
- FY2025 revenue US$122.42B (+35.9% YoY); Q4 2025 US$33.73B (~70.4% of global foundry revenue); Q1 2026 US$35.90B
- Employees
- 90,557 as of Dec 31, 2025; targeting ~100,000 by end-2026
- Major Segments
- AI accelerators/HPC, smartphone APs, automotive, IoT — the leading-edge slice specifically serves AI/HPC (AMD, Broadcom, NVIDIA) and flagship mobile
- Long-Term Strategy
- Extending its lead via N2 (HVM since Dec 2025) → A16 (2H2026, backside power) → A14 (~2027) → A12/A13/N2U roadmap through 2029; doubled fab-construction pace to ~9 phases/year in 2025-26
Process Technologies
| Process | Family | Architecture | Status | Details |
|---|---|---|---|---|
| A142028 · 300mm | Gate-all-around | Nanosheet GAA | Announced | Up to 15% speed improvement, up to 30% power reduction and >20% logic density vs N2. On track for 2028 per TSMC.HPC, AI accelerators |
| A162026 · 300mm | Gate-all-around | Nanosheet GAA with Super Power Rail (SPR) | Announced | Backside power delivery via Super Power Rail. 8-10% speed, 15-20% power reduction and up to 1.10x chip density vs N2P.HPC, AI accelerators |
| N22025 · 300mm | Gate-all-around | Nanosheet GAA | Volume production | TSMC's first move off FinFET, which had carried N7 through N3. Baseline for the N2 family.Smartphone, HPC |
| N2P2025 · 300mm | Gate-all-around | Nanosheet GAA | Volume production | 18% speed improvement or 36% power reduction, with 1.2x logic density and 1.15x chip density vs N3E.Smartphone, HPC |
| N3X2025 · 300mm | FinFET | FinFET, 2-fin standard cell | Volume production | 5% faster than N3P; up to 9% area reduction vs 3-2 fin FinFlex at equal speed.HPC |
| N4C2025 · 300mm | FinFET | FinFET | Risk production | Cost-optimised N4 variant. Risk production H1 2025.Cost-sensitive smartphone and consumer |
| N4X2024 · 300mm | FinFET | FinFET | Volume production | 6% speed gain vs N4P, accepting a leakage trade-off.HPC |
| N4P2023 · 300mm | FinFET | FinFET | Volume production | 11% performance boost vs N5.Smartphone, HPC |
| N32022 · 300mm | FinFET | FinFET | Volume production | Baseline of the N3 family.Smartphone, HPC |
| N42022 · 300mm | FinFET | FinFET | Volume production | Enhanced N5 with density improvement.Smartphone, HPC |
| N62020 · 300mm | FinFET | FinFET with EUV | Volume production | Power, performance and density improvement over N7 at similar defect density.Smartphone, IoT, consumer |
| N2XYear not recorded · 300mm | Gate-all-around | Nanosheet GAA, ultra-high-performance standard cell | Announced | Ultra-high-performance variant; combined 10% speed boost vs N2P.HPC, high-frequency designs |
| N3EYear not recorded · 300mm | FinFET | FinFET | Volume production | Design-rule baseline that N3P and the N2 family are benchmarked against.Smartphone, HPC |
| N3PYear not recorded · 300mm | FinFET | FinFET | Volume production | Optical shrink of N3E with additional performance, lower power and higher density. Compatible with N3E design rules; comparable yield.Smartphone, HPC |
| N5Year not recorded · 300mm | FinFET | FinFET with EUV | Volume production | Substantially improved power, performance and density vs N7. Baseline of the N5 family.Smartphone, HPC |
| N5PYear not recorded · 300mm | FinFET | FinFET with EUV | Volume production | Performance-enhanced N5, backward compatible with N5.Smartphone, HPC |
| N7Year not recorded · 300mm | FinFET | FinFET | Volume production | 30% speed improvement, 55% power saving and 3x logic density vs N16.Smartphone, HPC, automotive |
| N7+Year not recorded · 300mm | FinFET | FinFET with EUV | Volume production | TSMC's first EUV production process.Smartphone, HPC |
Technology Portfolio
- Most Advanced Node in HVM (mid-2026)
- N2 (2nm-class GAAFET) — volume production since Q4/Dec 2025, running in parallel at Fab 20 (Hsinchu Baoshan) and Fab 22 (Kaohsiung)
- Node Range Offered (≤22nm)
- N16 → N10 → N7 → N6/N5/N4 → N3(B/E/P) → N2 → A16 (2H2026)
- Transistor Architecture
- FinFET (N3 and above); GAA nanosheet from N2 onward
- Backside Power Delivery
- Yes — A16 'Super Power Rail', volume 2H2026
- In-House Advanced Packaging
- Yes — CoWoS, SoIC, InFO (deepest in the industry; CoWoS ~fully booked for ~1M wafers of 2026 demand)
- HBM Integration Support
- Yes — leading position, tight allocation (NVIDIA ~60% of CoWoS locked)
- Automotive/Defense-Qualified Advanced Node
- Yes — automotive-qualified N5/N3 variants
- Reported Yield (Most Advanced Node)
- ~90% at N2 (KeyBanc supply-chain data, mid-2026)
- Reported Density (Most Advanced Node)
- ~313 million transistors/mm² (high-density standard cells, N2)
- Next-Node Roadmap
- A16 (2H2026) → A14 (~2027, first High-NA EUV layers) → A12/A13/N2U through 2029
Manufacturing Capability
- Qualified Leading-Edge Fabs
- 7+ across Taiwan, US, Japan, Germany, China (Nanjing)
- Multi-Site Technology Transfer
- Yes — simultaneously ramping N2 at 3 facilities (Fab20 Hsinchu, Fab22 Kaohsiung), described as highly uncommon industry-wide
- Automotive/Defense Production
- Yes — automotive-qualified N5/N3 variants; defense linkage less publicly disclosed than Intel's
- IATF 16949
- Yes (verify per fab)
- Other Certifications
- ISO 9001 (verify per fab)
- Export Restriction Status
- Taiwan/US/Japan/Germany sites not export-restricted; Nanjing (China, 16/12nm) fab lost Validated End-User (VEU) status effective Dec 31, 2025 — individual US export licenses now required
Capacity & Supply Chain
- Backlog / Lead Time
- N2 reportedly sold out through Q2 2027; CoWoS advanced packaging booked for ~1M wafers of 2026 demand with NVIDIA holding ~60%
- Utilization & Yield Maturity
- N3 at full capacity since 2024; N2 ramping toward ~90,000-100,000 wpm by end-2026 across 2 facilities; company doubled fab-construction pace to ~9 phases/year in 2025-26 (vs. ~4 historically)
- Expansion Plans
- A16/A14 development; new Kaohsiung and Hsinchu Baoshan capacity; Arizona Fab 21 phases 2-3 (3nm/2nm/A16, equipment install 3Q2026); Kumamoto Fab 23 phase 2 (shifted to N3 for local demand)
- Geographic Redundancy
- Improving — Taiwan + Arizona (US) + Kumamoto (Japan) + Dresden (Germany), but still roughly 90%+ of actual leading-edge wafer starts remain Taiwan-based
- Single-Site Concentration Risk
- High — despite overseas diversification, the overwhelming majority of leading-edge volume is still produced in Taiwan
- Natural Disaster Exposure
- Elevated — Taiwan seismic/Strait risk applies to the bulk of actual leading-edge production
Fabs & Geopolitical Risk
| Fab Site | Country | US Import Tariff | Considerations | Risk |
|---|---|---|---|---|
| Fab 12, 14, 15, 18, 20, 22 — Hsinchu/Tainan/Taichung/Kaohsiung | Taiwan | Not recorded | Taiwan Strait tension; TSMC's concentration of leading-edge production is the core of the 'silicon shield' dynamic — simultaneously a deterrent and the industry's single largest point of failure | Elevated |
| Fab 16 — Nanjing (16/12nm) | China | Not recorded | Lost Validated End-User (VEU) status effective Dec 31, 2025; individual US export licenses now required for controlled equipment/software | High |
| Fab 21 — Phoenix, Arizona | United States | Not recorded | CHIPS Act award finalized at $6.6B (Nov 2024); 4nm HVM since early 2025; phase 2 (3nm/2nm) equipment install 3Q2026, pulled forward from 2028 to ~2027; phase 3 (2nm/A16) targeted before end of decade; total announced investment $165B | Low |
| ESMC — Dresden | Germany (EU) | Not recorded | EU Chips Act eligible; 28/22nm and 16/12nm, ~40,000 wpm, targeted at automotive/industrial legacy-adjacent nodes | Low |
| Fab 23 phase 2 — Kumamoto (JASM; construction paused late 2025, mass production now ~2029) | Japan | Not recorded | Japanese government covering ~40% of JASM's capital cost; phase 2 shifted from planned 6/7nm to N3 (3nm) to meet stronger-than-expected local demand | Low |
Cost & Commercial
- Approx. 300mm Wafer Price (Most Advanced Node)
- N3: ~$19,500-20,000; N2 not yet publicly benchmarked but expected above N3 given the historical step-up pattern (28nm $3,000 → 7nm $9,500 → 5nm ~$18,500 → 3nm ~$19,500-20,000)
- Approx. Mask Set Cost (Most Advanced Node)
- N3: ~$15-20M; figures above $20M have been cited for the most advanced nodes industry-wide
- Approx. Full Tapeout Cost (Design + Mask + NRE)
- 3nm-class SoC: approaching or exceeding $500M for complex designs (EDA, IP, mask, verification, NRE combined)
- MPW / Small-Program Access
- Minimal — direct TSMC engagement typically requires >1,000 wafers/year; smaller programs route through Value Chain Aggregator (VCA) partners like Global Unichip or Alchip
- Pricing Position
- Premium — sets the price ceiling that Samsung and Intel position against; brand and ecosystem depth command the premium
- Packaging Cost Add-On (CoWoS/HBM-Class)
- $500-$1,500+ per unit for CoWoS/HBM integration; can exceed the logic die's own cost for AI accelerators
Ecosystem
- Cadence
- Yes — full OIP certification
- Synopsys
- Yes — full OIP certification
- Siemens EDA (Calibre)
- Yes — Calibre standard sign-off
- Own Ecosystem Program
- OIP (Open Innovation Platform) — the largest certified third-party IP/EDA ecosystem of any foundry globally
- IP Vendor Relationships
- Hundreds of certified IP vendors (ARM and others) under OIP; broad chiplet/UCIe ecosystem support
- Advanced Packaging Partners
- In-house CoWoS/SoIC/InFO plus ASE, Amkor, and others
- Notable Ecosystem Note
- The de facto industry-standard ecosystem that Samsung and Intel both explicitly position against