← 200mm Mature-Node
TSMC (90nm-and-above scope only)
Hsinchu, Taiwan
Company Overview
- Headquarters
- Hsinchu, Taiwan
- Ownership
- Public (TWSE: 2330 / NYSE: TSM)
- Total Fabs
- 14 managed fabs per TSMC's 2025 Annual Report (9 in Taiwan: 4x 12-inch, 4x 8-inch, 1x 6-inch; plus Nanjing, Arizona, JASM Japan, TSMC Washington, TSMC China) — most run leading-edge nodes outside this database's scope
- 200mm Fab Locations
- 8-inch Fab 3/5/6/8 (Taiwan), Fab 10 (Shanghai, 8-inch), Fab 11 / WaferTech (Camas, WA, 8-inch); mature 12-inch lines at Fab 12/14/15/16. Note: SSMC (Singapore, 200mm) is a JV TSMC holds 38.8% of (NXP 61.2%) and is not counted among TSMC's own fabs
- Wafer Sizes Run
- 150mm/200mm & 300mm (this row covers only the 90nm-and-above portion of a company that also runs down to 2nm)
- Most Recent Revenue
- ~69.9% share of top-10 foundry revenue in 2025 per TrendForce (up from 64.4% in 2024; top-10 cohort totalled US$169.47B — this is not a share of the total global market). Whole-company FY2025 revenue US$122.42B. Annual capacity exceeded 17M 12-inch-equivalent wafers in 2025 across ALL nodes — mature-node share not broken out
- Employees
- 90,557 as of Dec 31, 2025 (whole company). TSMC's stated 2026 plan is ~8,000 new hires, implying ~98,000; the ">100,000 by 2026" figure is a third-party projection, not a TSMC statement
- Major Segments
- Whole company: HPC, smartphone, IoT, automotive, DCE. The 90nm+ slice specifically serves automotive, industrial, RF/mmWave, PMIC (BCD), and legacy consumer/CIS segments
- Long-Term Strategy
- Reallocating 40-90nm capacity toward CoWoS/advanced-packaging for AI, which is *tightening* mature-node supply industry-wide — a tailwind for GF/UMC/VIS/Tower/X-FAB. Still actively developing new 90nm+ specialty platforms (e.g., 90nm BCD in volume since 2024, 22nm BCD in development) rather than exiting the business, but is shrinking pure commodity legacy-logic volume
Process Technologies
No named process technologies recorded for this foundry yet.
Absence here means the process list has not been researched, not that the foundry offers none.
Technology Portfolio
- CMOS Min/Max Geometry
- 0.5um-90nm shown here (full company range extends to 2nm/N2, out of scope)
- CMOS Analog/RF/Mixed-Signal
- Yes — RF CMOS, mmWave
- CMOS Embedded Memory
- Yes — industry-leading eFlash/OTP/MTP, plus N12e RRAM, MRAM
- CMOS HV, Automotive-Qualified
- Yes (automotive-qualified, strong)
- BCD Voltage Range
- Yes — 0.18um BCD (established), 90nm BCD (volume production since 2024, targeting chargers/audio-amp ICs and now servers), 22nm BCD (in development)
- BCD LDMOS
- Yes
- BCD/SOI Isolation Option
- Yes
- SOI — PD-SOI
- Limited
- SOI — FD-SOI
- No (not a core TSMC offering)
- SOI — RF-SOI
- Yes
- SOI — Photonics-Compatible
- Emerging (COUPE / silicon-photonics R&D)
- MEMS
- Limited
- Power — SiC
- No
- Power — GaN
- Limited (GaN-on-Si specialty program)
- Power — HV CMOS
- Yes
- Specialty — eNVM
- Yes (industry-leading eFlash portfolio)
- Specialty — CIS
- Yes
- Specialty — Photonics
- Emerging
- Specialty — Display Driver
- Limited
Manufacturing Capability
- Qualified 200mm Fabs
- 4 (8-inch Fab 1-4, Taiwan) + Fab 10 (Shanghai, 8-inch) + WaferTech (Camas WA, 8-inch) + SSMC (Singapore, mixed) + mature portions of Fab 12/14/15/16
- Multi-Site Technology Transfer
- Yes — core competency; TSMC standardizes process transfer across its GIGAFAB network
- Automotive Production Volume
- Yes — major automotive supplier across 0.18um-16nm automotive-qualified nodes
- IATF 16949
- Yes
- ISO 13485 (Medical)
- Verify
- ISO 9001
- Yes
- AS9100 (Aerospace)
- Verify
- Defense / Rad-Hard Experience
- Limited disclosed
- Export Restriction Status
- Taiwan/US/Japan/Singapore sites not export-restricted; Nanjing (China) fab lost Validated End-User (VEU) status effective Dec 31, 2025 — individual US export licenses now required for controlled equipment/software
Capacity & Supply Chain
- Typical Quoted Lead Time (200mm)
- Not separately quoted for mature nodes — company-wide backlog typically longer than pure mature-node specialists; verify current
- Recent Utilization
- Company-wide record capacity in 2025 (>17M 12-inch-equivalent wafers); 40-90nm specifically being reallocated toward CoWoS/advanced packaging, which tightens available legacy supply even as overall utilization is high
- Expansion Plans
- Fab 15 (Taichung, 28-40nm, ~100K WPM) expanding; Kumamoto Fab 23 phase 1 (22/28nm) operating, phase 2 shifted toward N3 for local demand; Dresden ESMC (28/22/16/12nm) targeted ~2027
- Geographic Redundancy
- Improving overall (Taiwan + Japan + Germany + US + China + Singapore), but mature-node capacity is still majority Taiwan-concentrated
- Single-Site Concentration Risk
- Moderate for mature nodes specifically (more geographically spread than most pure-plays); overall company concentration in Taiwan remains high
- Natural Disaster Exposure
- Elevated for Taiwan-based mature lines (shared Strait/seismic risk with UMC/VIS); low at overseas mature sites (Japan, Germany, US, Singapore)
- Utility Risk (Power/Water)
- Moderate — Taiwan water/power constraints have affected the industry before; overseas mature sites are low risk
Fabs & Geopolitical Risk
| Fab Site | Country | US Import Tariff | Considerations | Risk |
|---|---|---|---|---|
| Fab 12/14/15 (mature 28-40nm portions) — Hsinchu/Tainan/Taichung | Taiwan | Not recorded | Same Taiwan Strait exposure as the 8-inch fabs; Fab 15's 28-40nm lines are a significant legacy-node source | Elevated |
| Fab 16 — Nanjing | China | Not recorded | Lost Validated End-User (VEU) status effective Dec 31, 2025; individual US export licenses now required for controlled equipment/software shipped to this site | High |
| Fab 10 — Shanghai | China | Not recorded | Same general China-siting export-control exposure as Nanjing; 8-inch mature-node production | High |
| JASM / Fab 23 phase 1 — Kumamoto | Japan | Not recorded | Low risk; strong Japanese government support and a local automotive/CIS customer base (Sony, Denso, Toyota JV partners) | Low |
| ESMC (Fab 23-equivalent) — Dresden | Germany (EU) | Not recorded | Low risk; EU Chips Act eligible, targeted at automotive/industrial legacy nodes (28/22/16/12nm), operational ~2027 | Low |
| Fab 11 / WaferTech — Camas, Washington | United States | Not recorded | Low export-control friction; aligned with US onshoring policy | Low |
| 8-inch Fab 3/5/6/8 — Hsinchu/Tainan (90nm+ scope) | Taiwan | Not recorded | Taiwan Strait tension; TSMC is the single most strategically significant company in this risk category (the 'silicon shield' dynamic) | Elevated |
| SSMC — Singapore (JV: TSMC 38.8%, NXP 61.2% — not counted among TSMC's own fabs) | Singapore | Not recorded | Low-risk, neutral jurisdiction; joint venture heritage with NXP | Low |
Cost & Commercial
- MPW Shuttle Availability
- Yes, indirectly — via EUROPRACTICE (Europe) and CMC Microsystems (Canada) academic brokers, and via design-service/VCA partners for commercial MPW, on select nodes (0.18um, 0.13um, 90nm)
- Typical Mask Set Cost (Order of Magnitude)
- Mature node (0.18um-90nm): moderate-to-high six figures — typically priced above pure mature-node specialists given TSMC's overall cost structure and brand premium
- Prototype/Engineering Wafer Pricing
- Not publicly listed; EUROPRACTICE/CMC provide the main academic/low-volume access path
- Production Wafer Pricing Direction (2025–26)
- TSMC raised prices at 5/4nm-and-below for 2026; 40-90nm lines are being reallocated toward CoWoS/packaging rather than repriced upward as aggressively — net effect is reduced available legacy supply more than a clean price signal
- Typical NRE Posture
- High — volume-production orientation; brand premium and large-customer focus generally price out very small programs relative to X-FAB/Tower/GF
- Packaging/Test Partnerships
- Deepest packaging ecosystem in this list — in-house 3DFabric/CoWoS/SoIC plus broad OSAT network (ASE, Amkor, and others)
- Licensing / IP Fees
- OIP (Open Innovation Platform) governs IP/EDA licensing; access still gated by TSMC's standard technology license agreement (TLA) process
Ecosystem
- Cadence
- Yes — full OIP certification across mature and advanced nodes
- Synopsys
- Yes — full OIP certification
- Siemens EDA (Calibre)
- Yes — Calibre is the standard sign-off tool
- Notable IP Vendor Relationships
- Largest certified third-party IP ecosystem of any foundry in this list (hundreds of vendors under OIP)
- OSAT / Packaging Partners
- ASE, Amkor, plus TSMC's own advanced packaging (CoWoS, SoIC, InFO) — the deepest packaging ecosystem in this list
- Design-Service Partners
- Global Unichip, Alchip, and other Value Chain Aggregator (VCA) partners; EUROPRACTICE/CMC Microsystems for academic access
- University / Reference-Design Programs
- EUROPRACTICE (Europe) and CMC Microsystems (Canada) broker MPW access to select TSMC mature nodes (0.18um, 0.13um, 90nm) for academic/low-volume use
- Open-Source / Academic PDK
- No public open PDK — EUROPRACTICE/CMC brokered academic access is the closest analog